Automatic synthesis and optimization of chip multiprocessors

The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental issue of power dissipation. Chip Multiprocessors (CMPs) have become the latest paradigm to improve the power-performance efficiency of computing systems by exploiting the parallelism inherent in applications. Industrial and prototype implementations have already demonstrated the benefits achieved by CMPs with hundreds of cores.CMP architects are challenged to take many complex design decisions. Only a few of them are:- What should be the ratio between the core and cache areas on a chip?- Which core architectures to select?- How many cache levels should the memory subsystem have?- Which interconnect topologies provide efficient on-chip communication?These and many other aspects create a complex multidimensional space for architectural exploration. Design Automation tools become essential to make the architectural exploration feasible under the hard time-to-market constraints. The exploration methods have to be efficient and scalable to handle future generation on-chip architectures with hundreds or thousands of cores.Furthermore, once a CMP has been fabricated, the need for efficient deployment of the many-core processor arises. Intelligent techniques for task mapping and scheduling onto CMPs are necessary to guarantee the full usage of the benefits brought by the many-core technology. These techniques have to consider the peculiarities of the modern architectures, such as availability of enhanced power saving techniques and presence of complex memory hierarchies.This thesis has several objectives. The first objective is to elaborate the methods for efficient analytical modeling and architectural design space exploration of CMPs. The efficiency is achieved by using analytical models instead of simulation, and replacing the exhaustive exploration with an intelligent search strategy. Additionally, these methods incorporate high-level models for physical planning. The related contributions are described in Chapters 3, 4 and 5 of the document.The second objective of this work is to propose a scalable task mapping algorithm onto general-purpose CMPs with power management techniques, for efficient deployment of many-core systems. This contribution is explained in Chapter 6 of this document.Finally, the third objective of this thesis is to address the issues of the on-chip interconnect design and exploration, by developing a model for simultaneous topology customization and deadlock-free routing in Networks-on-Chip. The developed methodology can be applied to various classes of the on-chip systems, ranging from general-purpose chip multiprocessors to application-specific solutions. Chapter 7 describes the proposed model.The presented methods have been thoroughly tested experimentally and the results are described in this dissertation. At the end of the document several possible directions for the future research are proposed

Static task mapping for tiled chip multiprocessors with multiple voltage islands

The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. Besides proposing a linear programming model for small systems, a novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing.Postprint (published version

Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

Abstract. The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple predefined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. A novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing

Surrogate-Assisted Evolutionary Generative Design Of Breakwaters Using Deep Convolutional Networks

In the paper, a multi-objective evolutionary surrogate-assisted approach for the fast and effective generative design of coastal breakwaters is proposed. To approximate the computationally expensive objective functions, the deep convolutional neural network is used as a surrogate model. This model allows optimizing a configuration of breakwaters with a different number of structures and segments. In addition to the surrogate, an assistant model was developed to estimate the confidence of predictions. The proposed approach was tested on the synthetic water area, the SWAN model was used to calculate the wave heights. The experimental results confirm that the proposed approach allows obtaining more effective (less expensive with better protective properties) solutions than non-surrogate approaches for the same time

Physical-aware link allocation and route assignment for chip multiprocessing

The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and the message routes for the traffic among the processing elements of the system. The solution of the problem meets the physical and performance constraints defined by the designer. The method guarantees that the generated solution is deadlock free. It is also capable of automatically discovering topologies that have been previously used in industrial systems. The applicability of the method has been validated by solving realistic size interconnect networks modeling the typical multiprocessor systems.Peer ReviewedPostprint (published version

Generative Design of Physical Objects using Modular Framework

In recent years generative design techniques have become firmly established in numerous applied fields, especially in engineering. These methods are demonstrating intensive growth owing to promising outlook. However, existing approaches are limited by the specificity of problem under consideration. In addition, they do not provide desired flexibility. In this paper we formulate general approach to an arbitrary generative design problem and propose novel framework called GEFEST (Generative Evolution For Encoded STructure) on its basis. The developed approach is based on three general principles: sampling, estimation and optimization. This ensures the freedom of method adjustment for solution of particular generative design problem and therefore enables to construct the most suitable one. A series of experimental studies was conducted to confirm the effectiveness of the GEFEST framework. It involved synthetic and real-world cases (coastal engineering, microfluidics, thermodynamics and oil field planning). Flexible structure of the GEFEST makes it possible to obtain the results that surpassing baseline solutions

Femtomolar detection of the heart failure biomarker NT-proBNP in artificial saliva using an immersible liquid-gated aptasensor with reduced graphene oxide

Measuring NT-proBNP biomarker is recommended for preliminary diagnostics of the heart failure. Recent studies suggest a possibility of early screening of biomarkers in saliva for non-invasive identification of cardiac diseases at the point-of-care. However, NT-proBNP concentrations in saliva can be thousand time lower than in blood plasma, going down to pg/mL level. To reach this level, we developed a label-free aptasensor based on a liquid-gated field effect transistor using a film of reduced graphene oxide monolayer (rGO-FET) with immobilized NT-proBNP specific aptamer. We found that, depending on ionic strength of tested solutions, there were different levels of correlation in responses of electrical parameters of the rGO-FET aptasensor, namely, the Dirac point shift and transconductance change. The correlation in response to NT-proBNP was high for 1.6 mM phosphate-buffered saline (PBS) and zero for 16 mM PBS in a wide range of analyte concentrations, varied from 1 fg/mL to 10 ng/mL. The effects of transconductance and Dirac point shift in PBS solutions of different concentrations are discussed. The biosensor exhibited a high sensitivity for both transconductance (2 uS/decade) and Dirac point shift (2.3 mV/decade) in diluted PBS with the linear range from 10 fg/mL to 1 pg/mL. The aptasensor performance has been also demonstrated in undiluted artificial saliva with the achieved limit of detection down to 41 fg/mL (~4.6 fM)

Comparative analysis of the scientific views of Russian and foreign scientists on the problem of training skilled judo wrestlers

We performed a comparative analysis of the scientific views of Russian and foreign scientists on the training activities of judo. Results were taken from scientific research performed by Russian and foreign scientists over the last 12 years. Using a structural analysis of important research work (articles and dissertations), we identified the main research directions of Russian scientists. We compared the results obtained with the scientific ideas of foreign experts. Our comparative analysis of the data showed that for some areas of wrestler training the views of Russian and foreign scientists significantly differ. There is a significant divergence of scientific views between Russian and foreign specialists in the sport of judo. This involved the problems of training athletes for competitive activities and the principles for selecting children and youths for judo during the initial stage of judo preparation